module MetalSense(
 input inLeft,inRight,clock,
 output led7,led6,
 output dirRt,dirLf
    );

/* HANDLED BY TankyTank
 reg rControl_1;
 reg lControl_1;
 reg rControl_2;
 reg lControl_2;
*/ 

reg dirRt_var;
reg dirLf_var;

 always @ (posedge clock)
 begin
 
 //metalDirRt metalDirLf directions
 // 1 = FWD
 // 0 = BKWD

  if(inLeft==1 && inRight ==0)
  begin //Right FWD; Left BKWD
   dirRt_var = 1;
   dirLf_var = 0;
  end
  
  else if (inLeft==0 && inRight==1)
  begin // Left FWD; Right BKWD
   dirRt_var = 0;
   dirLf_var = 1;
  end
  
  else if (inLeft==0 && inRight==0)
  begin // Left FWD; Right BKWD
   dirRt_var = 0;
   dirLf_var = 0;
  end
 
  else if (inLeft==1 && inRight==1)
  begin //Right & Left FWD
   dirRt_var = 0;
   dirLf_var = 0;
  end
  
 end
 
 assign led7 = inLeft;
 assign led6 = inRight;
 
 assign dirRt = dirRt_var;
 assign dirLf = dirLf_var;
 
/* --HANDLED BY TankyTank
  assign rC
 assign rC
 assign lC
 assign lC
*/ 

endmodule

module Tankytank(
 output [15:0] stepDelay,
   output [1:0]rControl,lControl,
 input clock,MetalDirRt,MetalDirLf
 );

//wire [15:0] stepDelay_wire;
// assign led0 = m;
//reg [15:0] stepDelay_var = 40000;
//reg fwd = ;
//reg bwd = 2'b01;

  // if (metaldetectorright == 1)
// begin
// assign stepDelay = 40000;
 
 
 reg [1:0] rControl_var;
 reg [1:0] lControl_var;
 reg stepDelayr_1;
 reg stepDelayl_1;

always @ (posedge clock)
begin 

 case (MetalDirRt)
   1'b1 : rC
  1'b0 : rC
 endcase

 case (MetalDirLf)
   1'b1 : lC
  1'b0 : lC
 endcase
 
end

  assign rC
 assign lC
 
 assign stepDelay = 40000;

endmodule