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Pasted as VHDL by freeone3000 ( 14 years ago )
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:48:16 11/29/2012 
-- Design Name: 
-- Module Name:    CarCounter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity CarCounter is
    Port ( clk : in  STD_LOGIC;
     reset : in STD_LOGIC;
           exit_c : buffer STD_LOGIC;
           enter_c : buffer  STD_LOGIC;

     
     -- physical pins
     LED : out std_logic_vector(7 downto 0);
     --RS232_DCE_TXD : out STD_LOGIC;
           BTN_WEST : in  STD_LOGIC;
           BTN_EAST : in  STD_LOGIC);
end CarCounter;

architecture LCD of CarCounter is
begin
end LCD;

architecture Behavioral of CarCounter is
 type state_type is (s1, s2, s3, s4, s5, s6, s7);
 signal current_s : state_type;
begin
 -- State change function
 process (clk, reset)
 begin
  if (reset = '1') then
   current_s <= s1;
   enter_c <= '0';
   exit_c <= '0';
  elsif (rising_edge(clk)) then
   enter_c <= '0';
   exit_c <= '0';
   if (current_s = s1) then
    if (BTN_EAST = '1') then
     current_s <= s2;
    elsif (BTN_WEST = '1') then
     current_s <= s5;
    end if;
   elsif (current_s = s2) then
    if (BTN_EAST = '1') and (BTN_WEST = '1') then
     current_s <= s3;
    elsif (BTN_EAST = '1') then
     current_s <= s2;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   elsif (current_s = s3) then
    if (BTN_EAST = '1') and (BTN_WEST = '1') then
     current_s <= s3;
    elsif (BTN_WEST = '1') then
     current_s <= s4;
    elsif (BTN_EAST = '1') then
     current_s <= s2;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   elsif (current_s = s4) then
    if (BTN_WEST = '0') and (BTN_EAST = '0') then
     enter_c <= '1';
     exit_c <= '0';
     current_s <= s1;
    elsif (BTN_WEST = '1') and (BTN_EAST = '1') then
     current_s <= s3;
    elsif (BTN_WEST = '1') then
     current_s <= s4;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   elsif (current_s = s5) then
    if (BTN_EAST = '1') and (BTN_WEST = '1') then
     current_s <= s6;
    elsif (BTN_WEST = '1') then
     current_s <= s5;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   elsif (current_s = s6) then
    if (BTN_EAST = '1') and (BTN_WEST = '1') then
     current_s <= s6;
    elsif (BTN_WEST = '1') then
     current_s <= s5;
    elsif (BTN_EAST = '1') then
     current_s <= s7;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   elsif (current_s = s7) then
    if (BTN_EAST = '0') and (BTN_WEST = '0') then
     enter_c <= '0';
     exit_c <= '1';
     current_s <= s1;
    elsif (BTN_EAST = '1') and (BTN_WEST = '1') then
     current_s <= s6;
    elsif (BTN_EAST = '1') then
     current_s <= s7;
    else
     current_s <= s1; -- Unknown or invalid state; reset.
    end if;
   end if;
  end if;
 end process;
 
 -- Count number of cars total
 process ( clk, reset )
  variable count : signed(7 downto 0) := "00000000";
 begin
  if (reset = '1') then
   count := "00000000";
  elsif (rising_edge(clk)) then
   if (enter_c = '1') then
    count := count + 1;
   elsif (exit_c = '1') then
    count := count - 1;
   end if;
   LED <= std_logic_vector(count(7 downto 0));
  end if;
 end process;
end Behavioral;

 

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