library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cetvorobitni_sb is
    Port ( iA : in  STD_LOGIC_VECTOR (3 downto 0);
           iB : in  STD_LOGIC_VECTOR (3 downto 0);
           oLED : out  STD_LOGIC_VECTOR (7 downto 0);
     iJOY : in STD_LOGIC_VECTOR (4 downto 0)
     );
   
end cetvorobitni_sb;

architecture Behavioral of cetvorobitni_sb is
 SIGNAL oS: STD_LOGIC_VECTOR (3 downto 0);
 SIGNAL oC: STD_LOGIC_VECTOR (3 downto 0);
 SIGNAL oLED1 : STD_LOGIC_VECTOR (7 downto 0);
 SIGNAL oLED2 : STD_LOGIC_VECTOR (7 downto 0);
 

begin

 --prvi sabirac

 oS(0) <= iA(0) xor iB(0) xor '0';
 oC(0) <= (iA(0) and iB(0)) or (iA(0) and '0') or (iB(0) and '0');
 
 --drugi sabirac
 
 oS(1) <= iA(1) xor iB(1) xor oC(0);
 oC(1) <= (iA(1) and iB(1)) or (iA(1) and oC(0)) or (iB(1) and oC(0));
 
 --treci sabirac
 
 oS(2) <= iA(2) xor iB(2) xor oC(1);
 oC(2) <= (iA(2) and iB(2)) or (iA(2) and oC(1)) or (iB(2) and oC(1));
 
 --cetvrti sabirac
 
 oS(3) <= iA(3) xor iB(3) xor oC(2);
 oC(3) <= (iA(3) and iB(3)) or (iA(3) and oC(2)) or (iB(3) and oC(2));
 
 oLED1 <= ("000" & oC(3) & oS); -- ukupna suma
 
 -- PRVI DODATAK
 
 oLED2 <= ("000" & oC(3) & oS) when iJOY="11111" else
    "00010001" when iJOY="01110" else
    "00100010" when iJOY="01101" else
    "01000100" when iJOY="01011" else
    "10001000" when iJOY="00111" else
    "11111111";
    
 -- DRUGI DODATAK
   
process(iA, iB, iJOY, oLED1, oLED2)
 begin
 case (iA(1 downto 0)) is
  when "00" => oLED <= oLED1;
  when "01" => oLED <= oLED2;
  when "10" => oLED <= iB & iA;
  when "11" => oLED <= ("0000000" & (iA(0) xor iA(1) xor iA(2) xor iA(3) xor iB(0) xor iB(1) xor iB(2) xor iB(3)));
  when others  => oLED <= "11111111";
 end case;
end process;
 

end Behavioral;