Psst.. new poll here.
Psst.. new forums here.
Microsoft is blocking us again (TY IP Reputation!) so just use oauth login instead. :)
Paste
Pasted as Verilog by sam373 ( 14 years ago )
module Register_File (A_addr,B_addr,operand,A_out,B_out,load);
input [2:0] A_addr;
input [2:0] B_addr;
input [1:0] load;
input [7:0] operand;
output [7:0] A_out;
reg [7:0] A_out;
output [7:0] B_out;
reg [7:0] B_out;
always@(A_addr or load)
if(A_addr<= 3'b000 && load<=1'b1) begin
A_out<=operand;
end
always@(B_addr or load)
if(B_addr<= 3'b001 && load<=1'b1) begin
B_out<=operand;
end
endmodule
Revise this Paste