FIFO0 : dcfifo_top 
   PORT MAP (
  data(8 downto 1) => TS1.data,--ts_ch2_data,
                data(0) => TS1.start,--ts_ch2_start,
  rdclk  => ts_asi_ref_clk,
  rdreq  => fifo_rdack,
  wrclk  => TS1.clk,--ts_ch2_clk,
  wrreq  => TS1.valid,--ts_ch2_valid,
  q(8 downto 1) => fifo_out,
                q(0) => fifo_out_start,
  rdusedw  => fifo_usedw
 );

-- Illegal TS1 in expression.
-- Record is declared like this:

type TS1 is record 
   clk   : std_logic;
   start : std_logic;
   valid : std_logic;
   data  : std_logic_vector(7 downto 0);
end record;