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Pasted as VHDL by scrts ( 12 years ago )
case(read_state) is
when start =>
if(mem_write = '0' and read_empty = '1') then -- if read FIFO is empty and other master is not writing...
mem_read_addr <= mem_read_addr + burstcount; -- unsigned + unsigned here
avm_memrd_burstcount <= std_logic_vector(burstcount); -- constant burstcount: 0x5E packets
mem_read <= '1';
read_state <= begin_read;
else
read_state <= start;
end if;
when begin_read =>
if(avm_memrd_waitrequest = '0') then -- Wait until slave will be ready...
mem_read <= '0'; -- and deassert the read signal
read_state <= end_read;
else
read_state <= begin_read;
end if;
when end_read =>
if(avm_memrd_readdatavalid = '1') then
if(read_valid_counter = 93) then
read_valid_counter <= (others => '0');
read_state <= start;
else
read_valid_counter <= read_valid_counter + 1;
read_state <= end_read;
end if;
end if;
end case;
--------------------------------------------------------------
-- The code that works, but not correctly:
case(read_state) is
when start =>
if(mem_write = '0' and read_empty = '1') then -- if read FIFO is empty and other master is not writing...
mem_read_addr <= mem_read_addr + burstcount; -- unsigned + unsigned here
avm_memrd_burstcount <= std_logic_vector(burstcount); -- constant burstcount: 0x5E packets
mem_read <= '1';
read_state <= begin_read;
else
read_state <= start;
end if;
when begin_read =>
if(avm_memrd_waitrequest = '0') then -- Wait until slave will be ready...
mem_read <= '0'; -- and deassert the read signal
read_state <= end_read;
else
read_state <= begin_read;
end if;
when end_read =>
--if(avm_memrd_readdatavalid = '1') then
if(read_valid_counter = 93) then
read_valid_counter <= (others => '0');
read_state <= start;
else
read_valid_counter <= read_valid_counter + 1;
read_state <= end_read;
end if;
--end if;
end case;
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