-- TS to IP siuntimo procedura UDP protokolu.

-- FIFO signalas FIFO_RDACK naudojamas kaip FIFO_RDREQ!!!
-- System clock = 85MHz
----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity avalon_switcher is
    Port ( 
     csi_clock     : in STD_LOGIC;
     csi_reset     : in STD_LOGIC;  
     -- Avalon-ST input from the IP to TS core
     asi_ts_ready    : out STD_LOGIC;
      asi_ts_channel   : in STD_LOGIC;
     asi_ts_data    : in STD_LOGIC_VECTOR(31 downto 0);
     asi_ts_valid    : in STD_LOGIC;  
     asi_ts_error    : in STD_LOGIC;
     asi_ts_empty    : in STD_LOGIC_VECTOR(1 downto 0);
     asi_ts_endofpacket  : in STD_LOGIC;
     asi_ts_startofpacket  : in STD_LOGIC;
     
     -- Avalon-ST input from the SGDMA
     asi_bus_ready   : out STD_LOGIC;
     asi_bus_data    : in STD_LOGIC_VECTOR(31 downto 0);
     asi_bus_valid   : in STD_LOGIC;  
     asi_bus_error   : in STD_LOGIC;
     asi_bus_empty   : in STD_LOGIC_VECTOR(1 downto 0);
     asi_bus_endofpacket : in STD_LOGIC;
     asi_bus_startofpacket : in STD_LOGIC;
     
     -- Avalon-ST output
     aso_ready    : in STD_LOGIC;
     aso_data    : out STD_LOGIC_VECTOR(31 downto 0);
     aso_valid    : out STD_LOGIC;
     aso_startofpacket  : out STD_LOGIC;
     aso_endofpacket  : out STD_LOGIC;
     aso_error    : out STD_LOGIC;
     aso_empty    : out STD_LOGIC_VECTOR(1 downto 0));
end  avalon_switcher;

architecture avalon_switcher of avalon_switcher is

signal ts_bus     : std_logic_vector(37 downto 0) := (others => '0');
signal ts_bus_pipelined : std_logic_vector(37 downto 0) := (others => '0');
signal dma_bus     : std_logic_vector(37 downto 0) := (others => '0');
signal dma_bus_pipelined : std_logic_vector(37 downto 0) := (others => '0');

begin
process(csi_clock,csi_reset) 
begin
 if(csi_reset='1') then
  aso_data <= (others => '0');
  aso_valid <= '0';
  aso_startofpacket <= '0';
  aso_endofpacket <= '0';
  aso_error <= '0';
  aso_empty <= (others => '0');
 elsif(rising_edge(csi_clock)) then
 
  ts_bus_pipelined <= ts_bus;
  dma_bus_pipelined <= dma_bus;
  
  if(asi_ts_channel='1') then
   asi_bus_ready   <= '0';
   asi_ts_ready   <= aso_ready;
   aso_data     <= ts_bus_pipelined(37 downto 6);
   aso_valid    <= ts_bus_pipelined(5);
   aso_error    <= ts_bus_pipelined(4);
   aso_empty    <= ts_bus_pipelined(3 downto 2);
   aso_startofpacket <= ts_bus_pipelined(1);
   aso_endofpacket   <= ts_bus_pipelined(0);
  else
   asi_bus_ready   <= aso_ready;
   aso_data     <= dma_bus_pipelined(37 downto 6);
   aso_valid    <= dma_bus_pipelined(5);
   aso_error    <= dma_bus_pipelined(4);
   aso_empty    <= dma_bus_pipelined(3 downto 2);
   aso_startofpacket <= dma_bus_pipelined(1);
   aso_endofpacket   <= dma_bus_pipelined(0);
  end if;
 end if; 
end process;

ts_bus  <= asi_ts_data  & asi_ts_valid  &  asi_ts_error  & asi_ts_empty  & asi_ts_startofpacket  & asi_ts_endofpacket;
dma_bus <= asi_bus_data & asi_bus_valid &  asi_bus_error & asi_bus_empty & asi_bus_startofpacket & asi_bus_endofpacket;

-- BYPASS SIGNALS
--aso_data <= asi_ts_data;
--aso_valid <= asi_ts_valid;
--aso_startofpacket <= asi_ts_startofpacket;
--aso_endofpacket <= asi_ts_endofpacket;
--aso_error <= asi_ts_error;
--aso_empty <= asi_ts_empty;
--asi_ts_ready <= aso_ready;

end avalon_switcher;