library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
--use std.textio.all;
--use ieee.std_logic_textio.all;

architecture sim_port_chan_splitter of port_chan_splitter is

component port_chan_splitter
 Port (
   csi_clk            : in std_logic;
   csi_reset          : in std_logic;
   
   asi_data           : in std_logic_vector(31 downto 0);
   asi_startofpacket  : in std_logic;
   asi_endofpacket    : in std_logic;
   asi_valid          : in std_logic;
   asi_empty          : in std_logic_vector(1 downto 0);
   asi_error          : in std_logic_vector(5 downto 0);
   asi_ready          : out std_logic;
   
   aso_data           : out std_logic_vector(31 downto 0);
   aso_startofpacket  : out std_logic;
   aso_endofpacket    : out std_logic;
   aso_valid          : out std_logic;
   aso_empty          : out std_logic_vector(1 downto 0);
   aso_error          : out std_logic_vector(5 downto 0);
   aso_channel        : out std_logic_vector(3 downto 0);
   aso_ready          : in std_logic
   );
end component;

constant T : time := 5 ns; 
signal clk : std_logic;
signal rst : std_logic;

signal asi_data           : std_logic_vector(31 downto 0) := (others => '0');
signal asi_startofpacket  : std_logic := '0';
signal asi_endofpacket    : std_logic := '0';
signal asi_valid          : std_logic := '0';
signal asi_empty          : std_logic_vector(1 downto 0) := (others => '0');
signal asi_error          : std_logic_vector(5 downto 0) := (others => '0');
signal asi_ready          : std_logic := '0';

signal aso_data           : std_logic_vector(31 downto 0) := (others => '0');
signal aso_startofpacket  : std_logic := '0';
signal aso_endofpacket    : std_logic := '0';
signal aso_valid          : std_logic := '0';
signal aso_empty          : std_logic_vector(1 downto 0) := (others => '0');
signal aso_error          : std_logic_vector(5 downto 0) := (others => '0');
signal aso_channel        : std_logic_vector(3 downto 0);
signal aso_ready          : std_logic := '0';

  
begin  
  
uut: work.port_chan_splitter
port map(
   csi_clk => clk,
   csi_reset => rst,
   
   asi_data => asi_data,
   asi_startofpacket => asi_startofpacket,
   asi_endofpacket => asi_endofpacket,
   asi_valid => asi_valid,
   asi_empty => asi_empty,
   asi_error => asi_error,
   asi_ready => asi_ready,
   
   aso_data => aso_data,
   aso_startofpacket => aso_startofpacket,
   aso_endofpacket => aso_endofpacket,
   aso_valid => aso_valid,
   aso_empty => aso_empty,
   aso_error => aso_error,
   aso_channel => aso_channel,
   aso_ready => aso_ready
  );

clkgen : process(clk) -- Generate clock
begin
    clk <= '1'; wait for T/2;
    clk <= '0'; wait for T/2;
end process;  

rst <= '1', '0' after 5*T/4; -- Generate reset


--process
--begin
--
--
--
--end process;

end sim_port_chan_splitter;