-- point_section.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity point_section is
 port (
  system_clock : in std_logic;
  global_reset : in std_logic;
  pt_clk : std_logic;
  enable : in std_logic;
  scan_rdy : in std_logic;
  angle_index : in std_logic_vector(work.pong_defs.SCANNER_ANGLE_INDEX_WIDTH-1 downto 0);
  distance_data : in std_logic_vector(work.pong_defs.SCANNER_DISTANCE_WIDTH-1 downto 0);
  section_out : out work.pong_defs.section;
  sect_debug_out : out work.pong_defs.section_debug;
  pos_rdy : out std_logic
 );
end entity;

architecture behavioral of point_section is
signal pt_clk_prev : std_logic;
signal first_point_found : std_logic;
signal rdy_delay : std_logic;
signal hold_pos_x, hold_pos_y : std_logic_vector(work.pong_defs.SCALING_WIDTH-1 downto 0);
signal debug_sig : std_logic;
begin
 rdy_sig_delay : entity work.signal_delay(behavioral)
 port map ( system_clock => system_clock, global_reset => global_reset,
 trigger_signal => rdy_delay, delayed_signal => pos_rdy );
 
 process (global_reset, pt_clk)
 begin
  if global_reset = '1' then
   pt_clk_prev <= '0';
   first_point_found <= '0';
   rdy_delay <= '0';
   hold_pos_x <= (others => '0');
   hold_pos_y <= (others => '0');
   pos_rdy <= '0';
   debug_sig <= '0';
   
  elsif rising_edge(system_clock) then
   -- if a new point arrived and it lies within our section (enable = '1')
   if pt_clk_prev = '0' and pt_clk = '1' and enable = '1' and first_point_found = '0' then
    -- check if point lies between 20cm and 30cm distance
    if unsigned(distance_data) >= 200 and unsigned(distance_data) <= 300 then
     hold_pos_x(work.pong_defs.SCANNER_ANGLE_INDEX_WIDTH-1 downto 0) <= angle_index;
     hold_pos_y(work.pong_defs.SCANNER_DISTANCE_WIDTH-1 downto 0) <= distance_data;
     first_point_found <= '1';
     rdy_delay <= '1';
    end if;
    debug_sig <= '1';
   end if;
   
   if pt_clk = '0' then
    pt_clk_prev <= '0';
    debug_sig <= '0';
   end if;
   
   -- reset signal of first_point_found after each scan cycle
   if scan_rdy = '1' then
    first_point_found <= '0';
   end if;
  end if;
 end process;
 
 section_out.pos.x <= hold_pos_x;
 section_out.pos.y <= hold_pos_y;
 sect_debug_out(0).gpos.x <= hold_pos_x;
 sect_debug_out(0).gpos.y <= hold_pos_y;
end architecture;


-- signal_delay.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signal_delay is
 generic (
  COUNTER_WIDTH : integer range 1 to 127 := 4;
  RISING_DELAY : integer range 1 to 8 := 2;
  FALLING_DELAY : integer range 1 to 8 := 4
 );
 port (
  system_clock : in std_logic;
  global_reset : in std_logic;
  trigger_signal : in std_logic;
  delayed_signal : out std_logic
 );
end entity;

architecture behavioral of signal_delay is
signal run_delay_counter : std_logic;
signal trigger_signal_prev : std_logic;
signal delay_cnt_val : std_logic_vector(COUNTER_WIDTH-1 downto 0);
begin
 delay_counter : entity work.counter(behavioral)
 generic map ( COUNTER_WIDTH )
 port map ( clk => system_clock, global_reset => global_reset,
 enable => run_delay_counter, reset => trigger_signal, 
 cnt => delay_cnt_val );
 
 count_ctrl : process (system_clock, global_reset)
 begin
  if global_reset = '1' then
   trigger_signal_prev <= '0';
   run_delay_counter <= '0';
   delayed_signal <= '0';
  elsif rising_edge(system_clock) then
   -- when trigger signal is detected, the counter is started
   if trigger_signal_prev = '0' and trigger_signal = '1' then
    trigger_signal_prev <= '1';
    run_delay_counter <= '1';
   end if;
   
   if trigger_signal = '0' then
    trigger_signal_prev <= '0';
   end if;
   
   -- the delayed signal will go high after RISING_DELAY clocks
   -- and go low again after RISING_DELAY+FALLING_DELAY clocks
   if unsigned(delay_cnt_val) > RISING_DELAY then
    if unsigned(delay_cnt_val) > RISING_DELAY+FALLING_DELAY then
     run_delay_counter <= '0';
     delayed_signal <= '0';
    else
     delayed_signal <= '1';
    end if;
   end if;
  end if;
 end process;
end architecture;