library ieee;
use ieee.std_logic_1164.all;

entity rng is
  port (
    clk   : in  std_logic;
    rbit  : out std_logic;
    valid : out std_logic;
  );
end rng;

architecture race of rng is
  signal r  : std_logic_vector(0 to 1) := "00";
  signal v1 : std_logic := '0';
  signal v2 : std_logic := '0';
begin

  RACE_PROC : process (r) is
  begin
  
    if r(0)'event and r(0) = '1' then
      if r(1) = '0' then
        rbit <= '0';
        v1   <= not v1;
      end if;
    end if;
    if r(0)'event and r(0) = '0' then
      if r(1) = '1' then
        rbit <= '0';
        v1   <= not v1;
      end if;
    end if;
    
    if r(1)'event and r(1) = '1' then
      if r(0) = '0' then
        rbit <= '1';
        v1   <= not v1;
      end if;
    end if;
    if r(1)'event and r(1) = '0' then
      if r(0) = '1' then
        rbit <= '1';
        v1   <= not v1;
      end if;
    end if;
    
  end process RACE_PROC;
  
  GEN_PROC : process (clk) is
  begin
    if clk'event and clk = '1' then
      if r = "00" then
        r <= "11";
      else
        r <= "00";
      end if;
      
      if v1 /= v2 then
        v2 <= v1;
        valid <= '1';
      else
        valid <= '0';
      end if;
    end if;
  end process GEN_PROC;
  
end architecture race;