library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity flvq is
 Port (clk : in STD_LOGIC;
   output : out STD_LOGIC_VECTOR(2 downto 0));
end flvq;

architecture Behavioral of flvq is
component ClusterLayer is
 Port ( Neuron_Input1,  Neuron_Input2, Neuron_Input3, Neuron_Input4,
    Neuron_Input5, Neuron_Input6, Neuron_Input7, Neuron_Input8, 
    Neuron_Input9: in  STD_LOGIC_VECTOR (11 downto 0);
      class_input : in STD_LOGIC_VECTOR (2 downto 0);
            clk : in  STD_LOGIC;
            similarity_max : out  STD_LOGIC_VECTOR (11 downto 0);
      class_output : out STD_LOGIC_VECTOR(2 downto 0));
end component;

component input_vec_ram is
 port (CLK  : in std_logic;
          WE   : in std_logic;
          EN   : in std_logic;
          ADDR : in std_logic_vector(5 downto 0);
          DI_1  : in std_logic_vector(11 downto 0);
    DI_2  : in std_logic_vector(11 downto 0);
    DI_3  : in std_logic_vector(11 downto 0);
          DO_1  : out std_logic_vector(11 downto 0);
    DO_2  : out std_logic_vector(11 downto 0);
    DO_3  : out std_logic_vector(11 downto 0));
end component;

signal tmp_in1 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in2 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in3 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in4 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in5 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in6 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in7 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in8 : std_logic_vector(11 downto 0):=x"000";
signal tmp_in9 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out1 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out2 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out3 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out4 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out5 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out6 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out7 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out8 : std_logic_vector(11 downto 0):=x"000";
signal tmp_out9 : std_logic_vector(11 downto 0):=x"000";
signal temp_sim_max : std_logic_vector(11 downto 0);
signal temp_class_output : std_logic_vector(2 downto 0);
signal addr : std_logic_vector(5 downto 0):="000000";

begin
Main1 : input_vec_ram port map (clk, '0', '1', addr, tmp_in1, tmp_in2, tmp_in3,
    tmp_out1, tmp_out2, tmp_out3);
Main2 : input_vec_ram port map (clk, '0', '1', addr, tmp_in4, tmp_in5, tmp_in6,
    tmp_out4, tmp_out5, tmp_out6);
Main3 : input_vec_ram port map (clk, '0', '1', addr, tmp_in7, tmp_in8, tmp_in9,
    tmp_out7, tmp_out8, tmp_out9);
Main4 : ClusterLayer port map (tmp_out1,tmp_out2,tmp_out3,tmp_out4,tmp_out5,tmp_out6,
           tmp_out7,tmp_out8,tmp_out9,"000",clk,temp_sim_max,temp_class_output);
           
output <= temp_class_output;

end Behavioral;