library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_addr1Bit is
end tb_addr1Bit;

architecture TEST of tb_addr1Bit is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
    return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  function INT (BIT : std_logic)
    return INTEGER is
  begin
    if bit = '1' then
      return 1;
    else
      return 0;      
    end if;
  end;

  -- Courtesy of http://www.edaboard.com/thread66558.html
  function INT (X : STD_LOGIC_VECTOR)
    return INTEGER is
    alias XV :std_logic_vector(X'length-1 downto 0) is X;
    variable accum : integer;
  begin
    accum := 0;
    for i in X'length-1 downto 0 loop
      accum := accum * 2;
      if X(i) = '1' then
        accum := accum + 1;
      end if;
    end loop;
    return accum;
  end;

  component addr1Bit
    PORT(
      A : in std_logic;
      B : in std_logic;
      Cin : in std_logic;
      S : out std_logic;
      Cout : out std_logic
      );
  end component;

-- Insert signals Declarations here
  signal A : std_logic;
  signal B : std_logic;
  signal Cin : std_logic;
  signal S : std_logic;
  signal Cout : std_logic;

-- signal <name> : <type>;

begin
  DUT: addr1Bit port map(
    A => A,
    B => B,
    Cin => Cin,
    S => S,
    Cout => Cout
    );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

  process
    variable iv : std_logic_vector(2 downto 0);
  begin

-- Insert TEST BENCH Code Here

    for k in 0 to 7 loop
      iv := INT_TO_STD_LOGIC(k,3);
      A <= iv(2);
      B <= iv(1);
      Cin <= iv(0);

      wait for 5 ns;

      assert(INT(Cout & S) /= (INT(A)+INT(B)+INT(Cin)))
        -- Courtesy of http://www.velocityreviews.com/forums/t22876-writing-to-stdout-in-vhdl.html
        -- I'm seriously using Velocity Reviews as a reference?
        report "Addition failure: "&integer;'image(INT(A))&"+"&integer;'image(INT(B))&"+"&integer;'image(INT(Cin))&" = "&integer;'image(INT(A)+INT(B)+INT(Cin))&" = "&integer;'image(INT(Cout&S)) severity error;

      wait for 5 ns;
    end loop;  -- k

  end process;
end TEST;

SIMULATION OUTPUT:

# ** Error: Addition failure: 0+0+0 = 0 = 0
#    Time: 5 ns  Iteration: 0  Instance: /tb_addr1bit
# ** Error: Addition failure: 1+1+1 = 3 = 3
#    Time: 75 ns  Iteration: 0  Instance: /tb_addr1bit