library ieee;
use ieee.std_logic_1164.all;

entity muxes is

  generic (
    CONF : natural := 1);
  port (
    clock  : in  std_logic;
    s1, s2 : in  std_logic;
    a, b   : in  std_logic_vector (15 downto 0);
    x, y   : out std_logic_vector (15 downto 0));

end muxes;

architecture test of muxes is

  signal xr, yr : std_logic_vector (15 downto 0);

begin  -- test

  mux : process (clock)
    variable u1, v1, u2, v2 : std_logic_vector (15 downto 0);
  begin  -- process mux
    if rising_edge(clock) then          -- rising clock edge

      if CONF = 1 then
        if s1 = '1' and s2 = '1' then
          u2 := yr;
          v2 := xr;
        elsif s1 = '1' then
          u2 := xr;
          v2 := yr;
        elsif s1 = '0' and s2 = '1' then
          u2 := b;
          v2 := a;
        else
          u2 := a;
          v2 := b;
        end if;
      end if;

      if CONF = 2 then
        if s1 = '1' then
          u1 := xr;
          v1 := yr;
        else
          u1 := a;
          v1 := b;
        end if;

        if s2 = '1' then
          u2 := v1;
          v2 := u1;
        else
          u2 := u1;
          v2 := v1;
        end if;
      end if;

      xr <= u2;
      yr <= v2;
    end if;
  end process mux;

  x <= xr;
  y <= yr;

end test;