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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:47:46 11/20/2010 
-- Design Name: 
-- Module Name:    rec2polar - final
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decoder is
 Port (  A : in std_logic_vector(4 downto 0);
    B : in  std_logic_vector(3 downto 0);
           F1 : out  std_logic_vector(6 downto 0);
     F2: out std_logic_vector(4 downto 0)
 );
end decoder;

architecture decoderbcd of decoder is
begin
 F2 <= A; -- "01111" Will set the first digit only. Falling edge active.
 with B select
  F1 <=  "0000001" when "0000",
     "1001111" when "0001", 
     "0010010" when "0010", 
     "0000110" when "0011", 
     "1001100" when "0100",
     "0100100" when "0101",
     "0100000" when "0110",
     "0001111" when "0111",
     "0000000" when "1000",
     "0000100" when "1001",
     "1111111" when others;
end decoderbcd;

entity rec2polar is
 Port ( X : in std_logic_vector(2 downto 0);
    Y : in std_logic_vector(2 downto 0);
    CLK : in std_logic;
    MAG : out std_logic_vector(5 downto 0);
    PHASE: out std_logic_vector(5 downto 0)
   );
end rec2polar;

architecture blackbox of rec2polar is
 type PROM_Array is array(63 downto 0) of std_logic_vector(5 downto 0);
 constant MAG_PROM: PROM_Array := (
  "000000","000001","000010","000011","000100","000011","000010","000001",
  "000001","000001","000010","000011","000100","000011","000010","000001",
  "000010","000010","000010","000011","000100","000011","000010","000010",
  "000011","000011","000011","000100","000101","000100","000011","000011",
  "000100","000100","000100","000101","000101","000101","000100","000100",
  "000011","000011","000011","000100","000101","000100","000011","000011",
  "000010","000010","000010","000011","000100","000011","000010","000010",
  "000001","000001","000010","000011","000100","000011","000010","000001"
 );
 constant PHASE_PROM: PROM_Array := (
  "001111","001111","001111","001111","101101","101101","101101","101101",
  "000000","000111","001010","001011","101111","110000","110001","110100",
  "000000","000100","000111","001001","110001","110010","110100","110111",
  "000000","000011","000101","000111","110011","110100","110110","111000",
  "000000","111001","110111","110101","000111","000110","000100","000010",
  "000000","111000","110110","110100","001000","000111","000101","000011", 
  "000000","110111","110100","110010","001010","001001","000111","000100",
  "000000","110100","110001","110000","001100","001011","001010","000111"
 ); 
 signal sig_xff, sig_yff : std_logic_vector(2 downto 0);
 signal sig_mag_out, sig_phase_out, sig_prom_input : std_logic_vector(5 downto 0);

begin

--  X Input D Latch (Clocked)
process(X, CLK)
begin
 if (rising_edge(CLK)) then
  sig_xff <= X;
 end if;
end process;

--  Y Input D Latch (Clocked)
process(Y, CLK)
begin
 if (rising_edge(CLK)) then
  sig_yff <= Y;
 end if;
end process;

process(sig_xff, sig_yff)
begin
 sig_prom_input <= sig_xff & sig_yff;
 sig_mag_out <= MAG_PROM(conv_integer(sig_prom_input));
 sig_phase_out <= PHASE_PROM(conv_integer(sig_prom_input));
end process;

process(sig_mag_out, CLK)
begin
 if (rising_edge(CLK)) then
  MAG <= sig_mag_out;
 end if;
end process;
  
process(sig_phase_out, CLK)
begin
 if (rising_edge(CLK)) then
  PHASE <= sig_phase_out;
 end if;
end process;

end blackbox;

entity main is
 Port ( X_PT : std_logic_vector(2 downto 0);
    Y_PT : std_logic_vector(2 downto 0);
    CLK_SIG  : std_logic_vector;
    LED : out  std_logic_vector(6 downto 0);
    DIGIT: out std_logic_vector(4 downto 0)
 );
end main;

architecture final of niggashit is
signal sig_mag_out, sig_phase_out : std_logic_vector(5 downto 0);

component rec2polar is
 Port ( X : in std_logic_vector(2 downto 0);
    Y : in std_logic_vector(2 downto 0);
    CLK : in std_logic;
    MAG : out std_logic_vector(5 downto 0);
    PHASE: out std_logic_vector(5 downto 0)
   );
end component;

component decoder is
 Port (  A : in std_logic_vector(4 downto 0);
    B : in  std_logic_vector(3 downto 0);
           F1 : out  std_logic_vector(6 downto 0);
     F2: out std_logic_vector(4 downto 0)
 );
end component;

begin

process(X_PT, Y_PT, CLK_SIG)
begin
 conversion : rec2polar port map(X_PT, Y_PT, CLK_SIG, sig_mag_out, sig_phase_out);
 digit1 : decoder port map("01111", '0' & sig_mag_out(5 downto 3), LED, DIGIT);
 digit2 : decoder port map("10111", '0' & sig_mag_out(2 downto 0), LED, DIGIT);
 digit3 : decoder port map("11011", '0' & sig_phase_out(5 downto 3), LED, DIGIT);
 digit4 : decoder port map("11101", '0' & sig_phase_out(2 downto 0), LED, DIGIT);
end process;

end final;

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