library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity ALU_24 is
    port (
        A: in UNSIGNED (3 downto 0);
        B: in UNSIGNED (3 downto 0);
        COP: in BIT;
        CLK: in BIT;
        RESET: in BIT;
        SNO: in BIT;
        RR: buffer UNSIGNED (7 downto 0);
        SKO: buffer BIT;
        PR: out UNSIGNED (1 downto 0)
    );
end ALU_24;

architecture ALU_24_arch of ALU_24 is

signal  RA: UNSIGNED (3 downto 0);
signal  RB: UNSIGNED (3 downto 0);
signal  SB: UNSIGNED (7 downto 0);
signal  SM: UNSIGNED (7 downto 0);
signal RSM: UNSIGNED (7 downto 0);
signal   P: BIT_VECTOR (3 downto 0);
signal  CS: INTEGER range 0 to 2;
signal  FC: BIT;
signal  EN: BIT;

begin
 TPO: process (RESET,CLK,SNO,SKO)
 begin
  if RESET = '1' then EN <= '0';
      elsif CLK'event and CLK = '1' then 
       if (SNO or SKO) = '1' then EN <= not EN;
         end if;
      end if;
 end process TPO;

 RGA: process (A,RESET,CLK,EN,COP)
 begin
  if EN = '0' then null;
      elsif CLK'event and CLK = '1' then
          if (P(0) = '1') and (COP='0') then RA <= A;
   elsif (P(0) = '1') and (COP='1') then RA <= "0000";
          end if;
      end if;  
 end process RGA;

 RGB: process (B,RESET,CLK,EN,COP)
 begin
  if EN = '0' then null;
      elsif CLK'event and CLK = '1' then
          if P(0) = '1' then RB <= B;
          elsif COP = '0' and P(2) = '1' then RB <= RB(3) & RB(3) & RB (2 downto 1);
          end if;
      end if;
 end process RGB;

 KS: process (RB,RR,COP)
 begin
  if COP = '0' then SB <= RR;
       elsif COP = '1' then SB <= RB(3) & RB(3) & RB(3) & RB(3) & RB(3) & RB(1) & RB(0) & RB(2);
       end if;
 end process KS;


 SM <= (("00" & RA(2 downto 0) & "000") + SB);

 RGR: process (CLK, EN, P, COP, P, RSM)
 begin
  if EN = '0' then null;
       elsif CLK'event and CLK = '1' then
          if P(0) = '1' then RSM <= "00000000";
          elsif COP = '0' and P(1) = '1' then RSM <= (RA(3) xor RB(3)) & '0' & SM (5 downto 0);
          elsif COP = '0' and P(2) = '1' then RSM <= RSM(7) & '0' & RSM (6 downto 1); --pravo
          elsif COP = '1' and P(1) = '1' then RSM <= SM;
   elsif COP = '1' and P(2) = '1' then RSM <= RSM(7) & RSM (7 downto 1); --pravo          
   elsif COP = '1' and P(3) = '1' then RSM <= RSM(7) & RSM (5 downto 0) & '0'; --levo
          end if;
       end if; 
  RR <= RSM;
 end process RGR;

 RPR: process (CLK, EN, P, COP)
 begin
  if EN = '0' then null;
       elsif CLK'event and CLK = '1' then
          if P(0)='1' and COP='1' then
           PR(1) <= (B(1) and not B(3)) or (B(0) and not B(3)) or B(2);
           PR(0) <= B(3) or B(2);
          end if; 
      end if;
 end process RPR;
 
 SKO <= ((not COP and P(2) and FC) or (COP and P(3)));

 DS: process (SNO, CLK, EN, COP, P)
 begin
  if SNO = '1' then P <= "0001";
      elsif EN = '0' then null;
      elsif CLK'event and CLK = '1' then
          if P(0) = '1' and B(0) = '1' and COP = '0' then P <= "0010";
          elsif P(0) = '1' and B(0) = '0' and COP = '0' then P <= "0100";
          elsif P(1) = '1' and COP = '0' then P <= "0100";
          elsif P(2) = '1' and RB(1) = '1' and COP = '0' then P <= "0010";
          elsif P(2) = '1' and RB(1) = '0' and COP = '0' then P <= "0100";
          elsif (COP = '1') and (P(0) = '1') then P <= "0010";
          elsif (COP = '1') and (P(1) = '1') then P <= "0100";
          elsif (COP = '1') and (P(2) = '1') then P <= "1000";
          end if;
      end if;
 end process DS;

 COUNTER: process (RESET, SNO, CLK, EN, COP, P, CS)
 begin    
  if SNO = '1' then CS <= 0;
      elsif CLK'event and CLK = '1' then
          if (EN and P(2) and (not COP)) = '1' then CS <= CS + 1;
          end if;
      end if;
      case CS is
         when 2 => FC <= '1';
         when others => FC <= '0';
      end case;
 end process COUNTER;
end ALU_24_arch;