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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:44:48 02/21/2008 
-- Design Name: 
-- Module Name:    nbcd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nbcd is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           x : in  STD_LOGIC;
           nut : out  STD_LOGIC);
end nbcd;

architecture Behavioral of nbcd is
type state_type is (A,B,C,D,E,F,G,H);
	signal state, nstate: state_type;
begin
	process(clk,reset) is
	begin
		if(clk'event and clk = '1') then
			if reset = '1' then state <= A;
			else
				state<=nstate;
			end if;
		end if;
	end process;

	process (state)is
	begin
		case state is
			when A =>
				nut <= '0';
				if (x = '0') then nstate <= B;
				else nstate <= C;
				end if;
			when B =>
				nut <= '0';
				nstate <= D;
			when C =>
				nut <= '0';
				if (x = '0') then nstate <= E;
				else nstate <= F;
				end if;
			when D =>
				nut <= '0';
				nstate <= G;
			when E =>
				nut <= '0';
				if (x = '0') then nstate <= G;
				else nstate <= H;
				end if;
			when F =>
				nut <= '0';
				nstate <= H;
			when G =>
				nut <= '0';
				nstate <= A;
			when H =>
				nut <= '1';
				nstate <= A;
		end case;
	end process;
end Behavioral;