library ieee;
use ieee.std_logic_1164.all;    
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clkdiv_TB is   -- entity declaration
end clkdiv_TB;

architecture TB of clkdiv_TB is

    component clkdiv_TB
    port(   T_clock_in: in std_logic;
           T_reset: in std_logic;
            T_clock_en: out std_logic
        );
    end component;
    
   signal T_clock_in : std_logic;
   signal T_reset : std_logic;
   signal T_clock_en : std_logic;

  begin
 
--U_clkdiv: clkdiv_TB port map (T_clock_in,T_reset,T_clock_en);
 
clock: process     
        begin
          T_clock_in <= '0';   -- clock cycle is 10 ns
          wait for 5 ns;
          T_clock_in <= '1';
          wait for 5 ns;
        end process;

--reset: process
--        begin
--         wait for 12 ns;
--         T_reset <= '1';
--         wait for 4 ns;
--         T_reset <= '0';
--         wait;
--       end process;
 
end TB;