library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


ENTITY display IS
 port (clk: in std_logic;
  getal: out std_logic_vector (6 downto 0);
  set: out std_logic_vector (3 downto 0));
END display;

architecture behav_int of display is
 signal teller : integer range 0 to 3 := 0;
 signal clk2 : std_logic;
 signal klokteller : integer range 0 to 400000 := 0;
begin

 process (clk)
 begin
 if rising_edge(clk) then
  if klokteller < 399999 then
   klokteller <= klokteller +1;
   clk2 <= '0';
  else
   klokteller <= 0;
   clk2 <= '1';
  end if;
 end if;
 end process;

 process (clk2)
 begin
  if rising_edge(clk2) then
   case teller is
    when 0 => teller <= 1;
    when 1 => teller <= 2;
    when 2 => teller <= 3;
    when others => teller <= 0;
   end case;   
   
  End if;
 end process;
 
 
 process (teller)
 begin  
  if teller = 1 then
   getal <= "0111111";
   set <= "1000";
  elsif teller = 2 then
   getal <= "1011111";
   set <= "0100";
  elsif teller = 3 then
   getal <= "1101111";
   set <= "0010";
  else
   getal <= "1110111";
   set <= "0001";
  end if;
 end process;
end;