module ask7(input [1:0]x, input reset, input clk, output reg z);

reg [1:0] state, nextstate;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

always @ (posedge clk, reset)
begin

if (reset==1) 
state <= S0; 
else 
state <= nextstate;
end

always @(*)
case (state)
    S0:  
    if      (x==2'b00) nextstate = S0; 
    else if (x==2'b01) nextstate = S0; 
    else if (x==2'b10) nextstate = S3; 
    else nextstate = S1;

    S1:  
    if      (x==2'b00) nextstate = S0; 
    else if (x==2'b01) nextstate = S0; 
    else if (x==2'b10) nextstate = S2; 
    else nextstate = S2;

    S2:  
    if      (x==2'b00) nextstate = S0; 
    else if (x==2'b01) nextstate = S0; 
    else if (x==2'b10) nextstate = S3; 
    else nextstate = S1;

    S3:  
    if      (x==2'b00) nextstate = S0; 
    else if (x==2'b01) nextstate = S0; 
    else if (x==2'b10) nextstate = S3; 
    else nextstate = S3;

default: nextstate = S0;
endcase

always @(state)
begin
case(state)

    S0: z=1'b0;
    S1: z=1'b0;
    S2: z=1'b1;
    S3: z=1'b1;      

default: z=1'b0;
endcase

end

endmodule