//clk_gen.v - generates a simple, digital clock w/ 50% duty-cycle
//
`timescale 1ns/1ns

module clk_gen(output clock);

    reg clock = 0;				//clock is initially 0

    always begin
    	#10 clock = ~clock;		//invert clock at 50% duty cycle
    end

  endmodule


//BCD_count.v - two-digit BCD counter
//
module BCD_count(input clock, input reset, output reg [7:0] BCD);

initial
	BCD = 8'b0000_0001;			//set initial value of BCD to 1

always @(posedge clock)
	begin
		if (~reset)				//if we get the signal reset the counter
			begin
			BCD[7:4] <= 4'b0000;
			BCD[3:0] <= 4'b0001;
			end

		else if (BCD[3:0] == 4'b1001) //roll BCD0 over after 9
			begin
			BCD[3:0] <= 4'b0000;
			if (BCD[7:4] == 4'b1001) 	//if BCD1 is also 9
				begin
				BCD[7:4] <= 4'b0000;	//reset counter
				BCD[3:0] <= 4'b0001;
				end
			else 
				BCD[7:4] <= BCD[7:4] + 4'b0001;	//otherwise, iterate BCD1
			end

		else 
			BCD[3:0] <= BCD[3:0] + 4'b0001;	//iterate BCD0
	end
endmodule


//tb_BCD_count.v - testbench for BCD counter
//
//should run for MAX_TICKS clocks
`timescale 1ns / 1ns

module tb_BCD_count();

parameter MAX_TICKS = 500;
reg sim_count = 0;

reg reset = 1;
wire clock;
wire [7:0] binary_result;

clk_gen U0 ( .clock(clock) );
BCD_count U1 ( .clock(clock), .reset(reset), .BCD(binary_result) );

initial
	begin
	$dumpfile("dumpvars.vcd");
        $dumpvars;
	$display("Begin Simulation");
	end

always @ (posedge clock)
	begin
	sim_count <= sim_count + 1;
	end

always @(*)
	if (sim_count > MAX_TICKS)
		begin
		$display("End Simulation");
		$finish;
		end

endmodule