module _design(
  output logic first,
  output logic second,
  output logic[1:0] all,
  input CLK,
);
  initial begin
    all[0] <= 0;
    all[1] <= 1;
  end

  always @(posedge CLK) begin
    first <= all [0];
    second <= all [1];
  end 
endmodule

module system(
  output logic lightLED1$_enable,
  output logic lightLED2$_enable,
  output logic lightLED3$_enable,
  input CLK,
);
  always @(posedge CLK) begin
    lightLED1$_enable <= first;
    lightLED2$_enable <= second;
    lightLED3$_enable <= all[1];
  end 
  _design _designInst(.CLK(CLK), .first(first), .second(second), .all(all));
endmodule