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# Create input clock, which is 100MHz
create_clock -period 10.000 -name clk100 [get_ports {clk100}]

# Do the PLL clock generation
derive_pll_clocks

# Derive clock uncertainty
derive_clock_uncertainty

# Create ethernet data rx clock, which can be 2.5MHz, 25MHz or 125MHz
create_clock -name enet_rx_clk_2M5 -period 400 [get_ports enet_rx_clk]
create_clock -name enet_rx_clk_25 -period 40 [get_ports enet_rx_clk] -add
create_clock -name enet_rx_clk_125 -period 8 [get_ports enet_rx_clk] -add
# Set the clocks as exclusive clocks
set_clock_groups -exclusive -group {enet_rx_clk_2M5} -group {enet_rx_clk_25} -group {enet_rx_clk_125}