Paste code

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

entity part1take2 is
 port( 
  CLOCK_50 : in std_logic;
  SW   : in unsigned(1 downto 0);
  LEDR  : out unsigned(8 downto 0)
 );
end part1take2;

architecture behavioral of part1take2 is 
 
 type statet is ( A, B, C, D, E, F, G, H, I );
 constant FMil: integer := 50000000;
 
 signal count : unsigned(25 downto 0);
 signal CLK  : std_logic;
 signal cstate, nstate : statet;
 signal lstate : unsigned(8 downto 0);
 
begin
 
 LEDR <= lstate;
 
 process(CLK, SW, cstate) 
 begin
  
  nstate <= cstate;
  LEDR <= to_unsigned(0, 9);
  
  if(SW(0) = '1') then
   nstate <= A;
  else 
   if(rising_edge(CLK)) then
    case cstate is
     when A =>
      lstate <= to_unsigned(000000001, 9);
      if(SW(1) = '1') then
       nstate <= F;
      else
       nstate <= B;
      end if;
     when B =>
      lstate <= to_unsigned(000000010, 9);
      if(SW(1) = '1') then
       nstate <= F;
      else
       nstate <= C;
      end if;
     when C =>
      lstate <= to_unsigned(000000100, 9);
      if(SW(1) = '1') then
       nstate <= F;
      else
       nstate <= D;
      end if;
     when D =>
      lstate <= to_unsigned(000001000, 9);
      if(SW(1) = '1') then
       nstate <= F;
      else
       nstate <= E;
      end if;
     when E =>
      lstate <= to_unsigned(000010000, 9);
      if(SW(1) = '1') then
       nstate <= F;
      else
       nstate <= E;
      end if;
     when F =>
      lstate <= to_unsigned(000100000, 9);
      if(SW(1) = '1') then
       nstate <= G;
      else
       nstate <= B;
      end if;
     when G =>
      lstate <= to_unsigned(001000000, 9);
      if(SW(1) = '1') then
       nstate <= H;
      else
       nstate <= B;
      end if;
     when H =>
      lstate <= to_unsigned(010000000, 9);
      if(SW(1) = '1') then
       nstate <= I;
      else
       nstate <= B;
      end if;
     when I =>
      lstate <= to_unsigned(100000000, 9);
      if(SW(1) = '1') then
       nstate <= I;
      else
       nstate <= B;
      end if;
    end case;
   end if;
  end if;
 end process;
 
 process(CLOCK_50) begin

  if rising_edge(CLOCK_50) then
   if(count = FMil) then
    CLK <= (not CLK);
    if(CLK = '1') then
     cstate <= nstate;
    end if;
   else 
    count <= count + 1;
   end if;
  end if;
 
 end process;
 
end behavioral;